Subthreshold Delay Variation Model Considering Transitional Region for Input Slew

Subthreshold design provides the promising advantage of low power consumption at cost performance variation and even circuit failure. An accurate efficient statistical timing model is crucial for analysis optimization guidance. Prior works lack consideration impact slew time or transitional region input due to process approaches considering load capacitance multiple variations in complex gates, resulting accuracy loss. In this work, an end gate delay analytically derived various slews capacitances. The between fast slow efficiently partitioned with adaptive error tolerance method so as characterize by linear interpolation based on that slew. order consider capacitance, relation sensitivity step dominant threshold voltage derived. For both parallel stacking structures are equivalently expressed from each transistor. proposed has been validated under advanced TSMC (Taiwan Semiconductor Manufacturing Company) 12 nm technology subthreshold achieves excellent agreement Monte Carlo SPICE (Simulation Program Integrated Circuit Emphasis) simulation results max less than 6.49% standard deviation 4.63%/6.40% max/min delay, demonstrating over 4 times precision improvement compared competitive analytical models.